PLL4 runs at 1.8GHz, /2 gives NCO clocks 0,1

Possible parent clocks:

# 62:  900000000 0 0xa0/0x23b040004: regval: 0x86100100 <- div 2 (PLL4 src)
# 63:  200000000 0 0xa0/0x23b040008: regval: 0x86100100 <- div 2 (PLL0/4 or PLL6/6 src?)

NCO clock inputs:

# 72:  900000000 0 0xa0/0x23b04002c: regval: 0x86100000
  User: /device-tree/arm-io/nco.clk[0]
# 73:  900000000 0 0xa0/0x23b040030: regval: 0x86100100 < div 2?
  User: /device-tree/arm-io/nco.clk[1]
# 74:  200000000 0 0xa0/0x23b040034: regval: 0x85100000
  User: /device-tree/arm-io/nco.clk[2]
# 75:  200000000 0 0xa0/0x23b040038: regval: 0x85100100 < div 2?
  User: /device-tree/arm-io/nco.clk[3]

NCOs:

NCO0: #155:  900000000 0 0xa8/0x23b044000: nco: 0x80000000 0x0 0x0 0x0 0x0 0x0 
NCO1: #156:  900000000 0 0xa8/0x23b048000: nco: 0x80300000 0x45e 0x5ad200 0xff9f5200 0x7f9f5200 0x0 
NCO2: #157:  900000000 0 0xa8/0x23b04c000: nco: 0x80000000 0x0 0x0 0x0 0x0 0x0 
NCO3: #158:  900000000 0 0xa8/0x23b050000: nco: 0x80000000 0x0 0x0 0x0 0x0 0x0 
NCO4: #159:  900000000 0 0xa8/0x23b054000: nco: 0x80000000 0x0 0x0 0x0 0x0 0x0 

MCA clock selects:

#112:  900000000 0 0xa0/0x23b0400d4: regval: 0x85100100 presume 5 = NCO0 / 2
#113:  900000000 0 0xa0/0x23b0400d8: regval: 0x86100000 presume 6 = NCO1 / 1
#114:  900000000 0 0xa0/0x23b0400dc: regval: 0x87100100 presume 7 = NCO2 / 2
#115:  900000000 0 0xa0/0x23b0400e0: regval: 0x88100100 presume 8 = NCO3 / 2
#116:  900000000 0 0xa0/0x23b0400e4: regval: 0x89100100 presume 9 = NCO4 / 2
#117:  900000000 0 0xa0/0x23b0400e8: regval: 0x89100100 presume 9 = NCO4 / 2

900000000 freqs seem like a lie here.